This invention relates to power MOSFETs having integrated control circuits on a common chip, and more particularly relates to a novel control circuit which prevents the false resetting of the control circuit fault latch, and which decouples the entire control circuit P well (in an N channel device) from the MOSFET body diode.
The device of application Ser. No. 08/121,288, referred to above, is a fully protected three-terminal monolithic "Smart Power" MOSFET that features overcurrent shutdown for short circuit protection and a gate-to-drain clamp for over-voltage protection. More specifically, the device is simply a power MOSFET with a control circuit powered from its gate-to-source voltage. This FET device is a "SMARTFET", a trademark of the International Rectifier Corporation, the assignee of the present invention. Within the control circuit are 1) an on/off circuit, or power MOSFET driver which responds to an externally applied input-to-source voltage, and the output of a logic circuit, 2) an overcurrent protection circuit, 3) an over-temperature protection circuit, and a logic circuit to process all of these control signals. In addition, the device contains an active drain-to-gate over-voltage clamp circuit. In either an over-temperature or overcurrent condition, a fault latch within the logic circuit is supposed to set, turning the power MOSFET off. Furthermore, this latch should remain set until the power MOSFET input-to-source voltage (which provides the power for the latch) is cycled to zero.
We have found that in certain applications, for example, when the power MOSFET is driving an inductive load in a "low side switch" configuration, and during a so-called "clamped inductive flyback" in response to an over-temperature condition in the power MOSFET that the fault circuit can be unintentionally reset even though the fault condition still exists.
More specifically, in the simple case of a grounded-source power MOSFET (without integrated control circuits), used as a d-c switch driving an inductive load which is tied between the MOSFET drain and a positive power supply, the sum of conduction and switching losses within the MOSFET could become high enough to drive the die junction temperature to a high enough value that the reliability of the device would suffer. With a SMARTFET device, however, if the power device junction temperature rises above a predefined threshold (typically 160.degree. C.), the control fault latch will set, pulling the MOSFET gate low, turning it off. Once the MOSFET gate has been pulled low, the current in the inductive load will need to decay, so the voltage across the load reverses (since V=Ldi/dt, and di/dt is negative), and the power MOSFET drain voltage will rise. In the absence of any clamping, and with a heavily inductive load, this drain voltage can rise until the power MOSFET drain-to-source junction breaks down, after which the decaying load current flows through the MOSFET drain-to-source junction.
Because power MOSFETs are not very rugged in this breakdown region of operation, SMARTFET devices have an active drain-to-gate clamp which turns the power MOSFET on when the drain-to-gate voltage exceeds a predetermined threshold, and at a drain-to-source voltage less than the breakdown voltage of the drain-to-source diode. In this way, the energy which can be absorbed by the power MOSFET (normally referred to as its "avalanche rating") may be greatly increased (by a factor of 10-100).
Accordingly, in the above-mentioned SMARTFET device over-temperature condition, the gate would initially be pulled low, the drain would go high (MOSFET off), and then the gate would be pulled high again by the drain-to-gate clamp (the drain-to-gate clamp overrides the fault latch signal). However, even while the drain-to-gate clamp and power MOSFET are on, the fault latch is required to maintain its "latched off" logic state, so that once the current in the inductive load has decayed to near zero, the drain voltage recovers with the power MOSFET off.
The problem we have observed is that once the load current has decayed sufficiently, the recovery of the drain voltage in a standard power MOSFET can, in certain applications, appear as a poorly damped oscillation which eventually settles out to the supply voltage and which can, in a transient mode, forward bias the drain-to-source body diode of the device. When this body diode is forward biased, parasitic inverse bipolar NPN action occurs between the drain/epi (NPN emitter) voltage, the control circuitry P well tied to the power MOSFET source (NPN base), and any N+ region at the surface of the semiconductor control circuit (multiple NPN collectors). The latter N+ regions could be formed, for example, by the drain or source regions of NMOS devices used in the control circuit. In the case of a typical NMOS inverter, such a parasitic NPN would cause the output of the inverter to become a logic low, regardless of its input voltage. The body diode conduction of the power MOSFET then causes the fault latch to be reset so that, after recovering from an over-temperature shutdown condition, the power MOSFET is on when it should be off, which defeats the purpose of over-temperature protection.